There is great interest in three dimensional (3D) heterogeneous integration (HI) technology in the integrated circuit industry, because with high heterogeneous device density in 3D integrated system, complex RF/mixed-signal ICs and systems can be achieved. Inevitably power density of an integrated system can easily exceed that of a conventional system, which can achieve up to an approximate value of 100 W/cm2. As more devices and functionalities are added, the power density increases, which can result in reduced device performance and shortened device lifetimes.
Heterogeneous integration of digital and non-digital devices into compact systems has a wide range of applications, including application in communication, automotive, environmental control, healthcare, security and entertainment. A few examples are phased array radars, high power transceivers, high power digital to analog converters (DACs), analog to digital converters (ADCs), and monolithic microwave integrated circuits (MMICs).
Much of prior art 3D integration effort has been focused on 3D silicon integration with through silicon vias (TSVs). The conventional thermal management approach for this effort is dissipating heat through copper (Cu) filled TSVs, as described in “Thermal Management of 3D IC Integration with TSV (Through Silicon Via)”, Electronic Components and Technology Conference, 2009. ECTC 2009. 59th and “Thermal analysis of a 3D die-stacked high-performance microprocessor”, GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI pp 19˜24.
The TSV method mainly extracts heat vertically and does not provide horizontal heat spreading. For the case of concentrated local heat generation often seen in heterogeneous integration, this method is not sufficient, because this method will simply transfer heat generated in a local hot spot in one layer to the level above or below resulting in other hot spots. Also for multiple chip stacking integration, chips that are stacked at higher level benefit less from this vertical thermal management solution.
For a bump bonding integration approach, there have been efforts to extract heat through bonding metal pads or metal interconnect lines, as described in “3D wafer-scale integration for RF and digital applications”, ECS Trans. 2008 volume 16, issue 8, 243-249. This approach also focuses on heat extraction through interconnect lines vertically and does not provide an adequate solution for local heat generation.
Another approach for cooling using interlayer fluid cooling technology for 3D integrated circuit packaging is described in “Interlayer Cooling Potential in Vertically Integrated Packages,” Microsystem Technol. 15(1) (2009) 57-74. This is a good packaging solution to extract heat from multiple stacked layers; however, this approach has increased costs, potential for a leak of cooling fluid, a system volume increase, and a questionable system lifetime.
For CMOS 3D integration, there is a prior art approach of fabricating thermal vias on a Si substrate and filling the vias with higher thermal conductivity metal, such as Cu. Such an approach has been described in “B. Goplen and S. S. Sapatnekar. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 25(4), pp. 692-709”, and “T. Y. Chian et al., Proc. IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, Calif., 2000, pp. 261-4”. Although this approach addresses vertical heat extraction, it does not provide for heat spreading. Also this approach is not applicable to integrated circuits with a silicon carbide (SiC) substrate, because SiC has a thermal conductivity similar to Cu, so a thermal via filled with Cu does not reduce thermal resistance, but rather increases thermal resistance due to the added thermal boundary resistance between Cu and SiC.
There have been efforts directed at growing a diamond layer on the back of a device, such as a Si, InP, or GaN device. The diamond layer acts as a heat spreading layer and has been described by SP3 Diamond. Technologies, for example, in a presentation titled “The Role of High Thermal Conductivity Substrates in Future CMOS Technologies” by Jerry Zimmer. This approach reduces the thermal resistance of native bulk substrates, such as Si, InP, and SiC by lowering junction temperatures. However, this approach is focused on low thermal resistance packaging approach for a single junction device, and maybe not be suitable as a growth platform or an integration platform due to the amorphous nature of this film and the high process temperature of diamond film.
What is needed is improved thermal management for multiple technology device technologies especially in the context of 3D integration. The embodiments of the present disclosure answer these and other needs.